Pedar, A and Jayanthi, J and Jyothi, N and Prasad, Renuka (1992) IPC Over Multibus-I for a QMR System. Technical Report. National Aerospace Laboratories, Bangalore, India.
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Abstract
The project Quadruple Redundant Fault Tolerant Computer System aims to develop expertise in the field of fault tolerant computing and development of highly reliable computing system by developing a benchtop model. The prototype system consists of four single board computers based on F9450A processors (Mil Std. Spec., 1750A13; Architecture) placed on the Multibus chassis. The four boards operate in Triple Modular Redundancy with comparison (TMR) with fourth one being a standby. Each board executes the same application task. For the purpose of voting, each board communicates its result to other boards. This requires interprocessor communication facility13; The F9450A board supports dual port RAM logic. RAM on each board is shared by other boards. The RAM on each board is assigned a Multibus Address. Communication is possible over the Multibus-I by means of this assigned multibus address. Modifications have been made in the hardware to enhance the addressing capability of the board from 64K to 1 megaword without actually using the memory management unit. A software package has been written in macro50 assembly language to accomplish the interprocessor communication facility.13;
| Item Type: | Monograph (Technical Report) |
|---|---|
| Uncontrolled Keywords: | Interprocessor communication;Dual port RAM;Fault tolerant computer system;SBC-50;MMU;Multibus-I;Memory architecture |
| Subjects: | MATHEMATICAL AND COMPUTER SCIENCES > Computer Operations and Hardware |
| Depositing User: | Mr. Ravikumar R |
| Date Deposited: | 02 Jun 2006 |
| Last Modified: | 24 May 2010 04:13 |
| URI: | http://nal-ir.nal.res.in/id/eprint/1710 |
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