Low sidelobe level microstrip patch array: Em design and performance analysis

Manohar, R and Dutta, M and Singh, Hema (2017) Low sidelobe level microstrip patch array: Em design and performance analysis. In: 2016 IEEE Annual India Conference, INDICON 2016, 16 - 18 December 2016, Bangalore, India.

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Abstract

A high performance low-profile antenna array with low sidelobe level (SLL) and optimum beamwidth is in general preferred in several communication related applications. In this paper a planar microstrip array antenna with low SLL up to -20 dB and high gain performance is designed for 10 GHz. The dimensions of patch antenna is tapered to achieve low SLL. The results for patch array with individual feed and a common feed are presented.

Item Type: Conference or Workshop Item (Paper)
Subjects: ENGINEERING > Communications and Radar
ENGINEERING > Electronics and Electrical Engineering
Depositing User: Mrs SK Pratibha
Date Deposited: 21 May 2020 11:12
Last Modified: 21 May 2020 11:12
URI: http://nal-ir.nal.res.in/id/eprint/13313

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