Design and implementation of ethernet based analyzer for avionics serial bus on FPGA

Tamrakar, I and Ananda, CM and Pradeep Kumar, B and Sree Ramani, PS (2017) Design and implementation of ethernet based analyzer for avionics serial bus on FPGA. In: 2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings, 20 - 21 May 2016, Bangalore, India.

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Abstract

Serial communication for transmission of data between the systems is predominantly used in avionics for decades due to its simplicity and low cost. This paper presents the design and implementation of ethernet based analyzer for analyzing dual speed avionics serial protocol. The analyzer performs analysis on each data packet with time stamping. It evaluates the detailed information about the received serial data. This dual speed serial bus analyzer is beneficial for traffic analysis during real time communication in avionics systems for critical analysis of data packet. The protocol analyzer is capable of handling received data stream with speed of 100kbps and 12.5kbps. Eight channels are supported for simultaneous processing by the protocol analyzer. It supports simultaneous processing for data packet analysis and time stamping information of each independent channel. Analyzer is connected to the host for analyzing the received data packet through ethernet communication. The TEMAC IP core for this proposed work has been developed in Xilinx tool and implemented on Xilinx Spartan 6 FPGA board.

Item Type: Conference or Workshop Item (Paper)
Subjects: AERONAUTICS > Avionics & Aircraft Instrumentation
ENGINEERING > Electronics and Electrical Engineering
Depositing User: Mrs SK Pratibha
Date Deposited: 25 Feb 2020 14:25
Last Modified: 25 Feb 2020 14:25
URI: http://nal-ir.nal.res.in/id/eprint/13250

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