Design of graphics processing framework on FPGA

Ramanathan, SG and Pradeep Kumar, B and Jayakumar, EP and Ananda, CM (2017) Design of graphics processing framework on FPGA. In: 2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings, 20 - 21 May 2016, Bangalore, India.

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Abstract

High performance graphics processing is a challenging task in embedded system domain. Field Programmable Gate Array (FPGA) attracts a great interest in building Graphics Processing Unit (GPU) framework on its platform due to its feasibility and configurable resources. This paper provides design perspectives of GPU framework and its building blocks to realize GPU functionality on FPGA to draw base primitives. In this proposal, triple video display buffers has been designed and implemented for buffering entire video frames in cyclic manner. The GPU framework IP core for the proposed approach has been designed and developed using Xilinx tools and has been implemented and tested using a Xilinx SP605 FPGA evaluation board. The IP Core is commanded from host system. Hardware Description Language (VHDL) has been used for design of GPU framework. This paper provides design and implementation details of basic building blocks required to achieve GPU functionalities on FPGA.

Item Type:	Conference or Workshop Item (Paper)
Subjects:	AERONAUTICS > Avionics & Aircraft Instrumentation ENGINEERING > Electronics and Electrical Engineering
Depositing User:	Mrs SK Pratibha
Date Deposited:	25 Feb 2020 14:25
Last Modified:	25 Feb 2020 14:25
URI:	http://nal-ir.nal.res.in/id/eprint/13248

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