Power Analysis of Low Power Virtex 6 FPGA based Communication FloSwitch Design

Jagannadham, VV and Sivaramakrishnan, Rajalakshmy (2013) Power Analysis of Low Power Virtex 6 FPGA based Communication FloSwitch Design. International Journal of Engineering Research and Technology, 2 (11). pp. 233-243. ISSN 2278-0181

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      Abstract

      Flosolver designed and developed Mk 8 parallel super computer with computing power of 10 TFLOPS. Mk8 used 1024 processor as processing elements (PE’s). Communication device called FloSwitch used for Data transfer across the processing elements [1]. Communication speed, power utilization and flexibility in the interconnectivity have always scope of improvement. In this report Power section has been addressed to improve further by bringing down the total power in the FloSwitch design. Theoretical analysis has been done to reduce FloSwitch power as a whole. Major change in the design is to replace external DPM with internal memory of FPGA (BLOCK RAM). Power analysis has been done on low power Virtex 6 FPGA and Virtex 5 FPGA using Xilinx power estimator (XPE) and power calculation for the entire board. FPGA’s power utilization has been analyzed in detail and overall board power calculations have been done. Comparative analysis results give the considerable power reduction for the new design.

      Item Type: Journal Article
      Additional Information: Copyright to this article belongs to M/s. IJERT
      Uncontrolled Keywords: FloSwitch;XPE;DPM;Block Ram;Optical links
      Subjects: ENGINEERING > Electronics and Electrical Engineering
      Division/Department: Flosolver Division , Flosolver Division
      Depositing User: Ms. Alphones Mary
      Date Deposited: 29 Jul 2015 10:38
      Last Modified: 29 Jul 2015 10:38
      URI: http://nal-ir.nal.res.in/id/eprint/12261

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